The present invention relates to semiconductor memories and particularly to their address decoder circuits.
The conventional 1 of N decoder dissipates large amounts of power due to its NOR configuration. The state-of-the-art decoders as used in static random access memories use a power down technique where a low Vt enhancement device whose gate is controlled by the chip-select signal is used as a switch to VDD. This decoder design helps eliminate the decoder power dissipation during standby mode. However, during the active cycle the whole array of decoders is powered up by the chip-select signal and all but the selected decoder NOR circuit dissipate power. The disadvantage of the power-up transistor used as a switch to VDD is that the NOR output high level is degraded, due mainly to the Vt drop. FIG. 1 and FIG. 2 show the conventional NOR decoder and the state-of-the-art decoder respectively. Many different versions of the state-of-the-art decoder design are commercially used. One of them reduces power by reducing the number of decoders to half and switching each decoder for two outputs using an additional input bit.
The decoder circuit of the present invention differs from the conventional (and the state-of-the-art) circuits in that the proposed circuit uses a power up device to VSS and that the driver circuits of unselected decoders do not dissipate any power during an active cycle. The ANDing function of the NOR output and the power up signal is accomplished in the driver stage of this circuit. This driver stage employs a reliable push-pull output section.
Thus it is an object of the present invention to provide a decoder having minimal power consumption at no speed penalty.
It is a further object of the present invention to provide a semiconductor random access memory having minimal power consumption.
It is a further of object of the present invention to provide a semiconductor random access memory having minimal power consumption in ecoder circuits thereof.
According to the present invention there is provided:
a NOR circuit, said NOR circuit comprising a plurality of field effect transistors in parallel, each field effect transistor comprising a gate terminal and first and second source/drain terminals, all of said respective first source/drain terminals of said transistors in said NOR circuit being connected together, and all of said second source/drain terminals of said transistors in said NOR circuit being connected together, said gates of said NOR circuit transistors each being connected to a respective single address bit; PA1 said first source-drain terminals of said NOR circuit transistors being operatively connected to receive a first power supply voltage; PA1 said second terminals of said NOR circuit transistors being operatively connected through a power-up transistor to a second supply voltage, said second supply voltage being lower in voltage than said first supply voltage.